1. Field of the Invention
The present invention relates to a delay circuit and a video signal processing circuit using the delay circuit.
2. Description of the Related Art
Analog color television systems which are employed in the world are broadly divided into three systems, i.e., NTSC (National Television Standards Committee) system employed mainly in Japan and North/Central America, PAL (Phase Alternation by Line) system employed mainly in the West European countries, and SECAM (SEquential Couleur A Memoire) system employed mainly in the East European countries. The NTSC system is a system of an interlaced scanning of 30 frames/sec, each frame having 525 horizontal scanning lines, with a horizontal scanning frequency at 15.75 kHz and with a vertical scanning frequency at 60 Hz. The PAL system is a system of an interlaced scanning of 25 frames/sec, each frame having 625 horizontal scanning lines, each of which is phase-inverted. The SECAM system is a system of an interlaced scanning of 25 frames/sec, each frame having 625 horizontal scanning lines. In this manner, all the systems of the NTSC, PAL, and SECAM basically perform the interlaced scanning and, as shown in FIG. 8, transmit one screen by two separate scan of one frame for an odd-numbered field and for an even-numbered field. The one frame consists of the odd-numbered field and the even-numbered field. More specifically, in the interlaced scanning, all the scanning lines in the odd-numbered field are scanned every alternate scanning line from top to bottom of the screen. The scanning of the last scanning line in the odd-numbered field is then discontinued halfway and all the scanning lines in the even-numbered field are scanned from top to bottom as if the interstices of all the scanning lines in the odd-numbered field are filled up.
In the NTSC, PAL, and SECAM systems, video signals of R (red), G (green), and B (blue) captured as an image by a television camera are not transmitted in their original forms, but there is employed a scheme of converting the video signals captured as an image into a luminance signal Y representing brightness of the screen and a chroma signal C representing the level of shading of the screen color, and further of transmitting a composite signal SC which is obtained by compositing the luminance signal Y and the chroma signal C. FIG. 9 shows examples of waveforms of a chroma signal C, a luminance signal Y, and a composite signal SC. The chroma signal C shown in (A) of FIG. 9 is a signal obtained by converting two color-difference signals R-Y and B-Y, which are obtained by subtracting the luminance signal Y from the R signal and B signal, respectively, into mutually orthogonal I-Q signal (case of NTSC system ) or U-V signal (case of PAL system) and by compositing and amplitude modulating the signals. The chroma signal C includes a color burst signal BS and a carrier chrominance signal CA. Note that the color burst signal BS is a signal used as a reference of the phase and amplitude of the carrier chrominance signal CA, and that the carrier chrominance signal CA is a signal with a phase thereof indicative of a hue and with an amplitude thereof indicative of chroma. The luminance signal Y shown in (B) of FIG. 9 includes a horizontal synchronizing signal HSYNC and a luminance signal YA. Note that the horizontal synchronizing signal HSYNC is a signal indicative of the start of a single scanning line in the horizontal direction, and that the period between the two adjacent horizontal synchronizing signals HSYNC is called “1H period (one horizontal scanning period: about 64 μsec)”. The luminance signal YA is a signal indicative of the details of the luminance. The composite signal SC shown in (C) of FIG. 9 is a composite of the chroma signal C shown in (A) of FIG. 9 and the luminance signal Y shown in (B) of FIG. 9. More specifically, the composite signal SC has a waveform obtained by superimposing the color burst signal BS of the chroma signal C on the back porch of the luminance signal Y and by superimposing the carrier chrominance signal CA of the chroma signal C on the luminance signal YA.
By the way, the overseas PAL and SECAM systems require the video signal processing circuit on the receiving side to delay color-difference signals R-Y and B-Y demodulated from video signals received at the antenna by 1H period and to combine the 1H-period delayed signals with the most recent color-difference signals R-Y and B-Y, to thereby eliminate distortions arising on transmission paths and to thereby match the color-difference information of all the scanning lines by line correction. The mainstream of such a circuit for delaying by 1H period (hereinafter, referred to as a 1H-delay circuit) has hitherto been of a type using CCD (Charged Coupled Device) delay elements (see, e.g., Japanese Patent Application Laid-Open Publication No. 1997-191472).
However, although the video signal processing circuit except the CCD delay element for 1H-delay circuit has hitherto been designed and manufactured exclusively by a bipolar process capable of handling analog signal easily, a shift to the next-generation BiCMOS process capable of handling both the bipolar and CMOS would enable the video signal processing circuit inclusive of the CCD delay element to be made into one chip for low-cost designing and manufacturing. It is also proposed to use as the 1H-delay circuit instead of the CCD delay element a “switched capacitor circuit” that is more inexpensive than the CCD delay element and that has hitherto been used dedicatedly as an analog filter.
FIG. 10 shows a configuration of a conventional delay circuit using the switched capacitor circuit. Note that although the delay circuit shown in FIG. 10 includes two switched capacitor units for simplification of explanation, the number of the switched capacitor units may vary depending on the delay time required.
NMOS transistors M1 and M2 have their respective source electrodes that are connected in common to a capacitive element C1 to make up a single switched capacitor unit 703a. Similarly, NMOS transistors M3 and M4 have their respective source electrodes that are connected in common to a capacitive element C2 to make up a single switched capacitor unit 703b. Note that an input voltage VIN to be delayed is applied to drain electrodes of the NMOS transistors M1 and M3, whilst the drain electrodes of the NMOS transistors M2 and M4 are connected to a non-inverting input terminal of a voltage follower 702.
That is, in the switched capacitor unit 703a, the NMOS transistor M1 functions as a charging MOS transistor for charging the capacitive element C1 based on an input signal IN, and the NMOS transistor M2 functions as a discharging MOS transistor for discharging the capacitive element C1 so that an output signal OUT is output. In the switched capacitor unit 703b, the NMOS transistor M3 functions as a charging MOS transistor for charging the capacitive element C2 based on the input signal IN, and the NMOS transistor M4 functions as a discharging MOS transistor for discharging the capacitive element C2 so that the output signal OUT is output.
Such a delay circuit further includes a switching control circuit 701 for performing on/off control of gate electrodes of the NMOS transistors M1 to M4. Note that the switching control circuit 701 inputs a switch signal SW1 to a gate electrode of the NMOS transistor M1, inputs switch signals SW2 to gate electrodes of the NMOS transistors M2 and M3, and inputs a switch signal SW3 to a gate electrode of the NMOS transistor M4. Such a configuration allows the voltage follower 702 to output an output voltage VOUT that is delayed from the input voltage VIN by a period of switching cycle of the NMOS transistors M1 to M4.
FIG. 11 is timing chart showing operation examples of the delay circuit shown in FIG. 10. Note that the level of the input voltage VIN is assumed to shift from D0 to D4 in respective periods segmented by times T0 to T5 (see (A) of FIG. 11), and that respective periods segmented by times T0 to T5 are correlated with the period of switching cycle of the NMOS transistors M1 to M4.
First, at time T0, the switching signals SW1 to SW3 input to the gate electrodes of the NMOS transistors M1 to M4 become at low, high, and low, respectively, and keep those states till time T1 (see (B) to (D) of FIG. 11). That is, at time T0, the NMOS transistors M1 and M4 are turned off and the NMOS transistors M2 and M3 are turned on, being kept in those states till time T1 (see (E) to (G) of FIG. 11). Thus, there is formed a charging path of the NMOS transistor M3 and the capacitive element C2 in the period of time T0 to T1, with the result that electric charge corresponding to the level D0 of the input voltage VIN in such a period is charged into the capacitive element C2 via the NMOS transistor M3, to thereby cause information on the level D0 of the input voltage VIN to be held (see (I) of FIG. 11). On the other hand, there is formed a discharging path of the NMOS transistor M2 and the capacitive element C1, while any electric charge is not yet held on the capacitive element C1 (see (H) of FIG. 11) with the output voltage VOUT remaining uncertain (see (J) of FIG. 11).
Next, at time T1, the switch signals SW1 to SW3 input to the gate electrodes of the NMOS transistors M1 to M4 become at high, low, and high, respectively, and keep those states till time T2 (see (B) to (D) of FIG. 11). That is, at time T1, the NMOS transistors M1 and M4 are turned on and the NMOS transistors M2 and M3 are turned off, being kept in those states till time T2 (see (E) to (G) of FIG. 11). Thus, in the period of time T1 to T2, there is formed a charging path of the NMOS transistor M1 and the capacitive element C1, with the result that electric charge corresponding to the level D1 of the input voltage VIN in such a period is charged into the capacitive element C1 via the NMOS transistor M1, to thereby cause information on the level D1 of the input voltage VIN to be held (see (H) of FIG. 11). On the other hand, there is formed a discharging path of the NMOS transistor M4 and the capacitive element C2, with the result that electric charge held on the capacitive element C2 is discharged to thereby cause the input voltage VIN of the level D0 corresponding to the electric charge to be read out (see (I) of FIG. 11) and to be applied to the non-inverting input terminal of the voltage follower 702. This allows the voltage follower 702 to output the output voltage VOUT that is delayed from the input voltage VIN of the level D0 by a period of switching cycle of the NMOS transistors M1 to M4 (see (J) of FIG. 11). Then, afterward, the above operation is repeated in each of periods of time T2 to T3, time T3 to T4, and time T4 to T5.
By the way, the NMOS transistors M1 to M4 exhibit in general a so-called well-type sectional structure as shown in FIG. 12. That is, polycrystalline polysilicon 13 is formed on a p-type silicon substrate 16 via silicon dioxide (SiO2) 14 for gate insulating film, on top of which polycrystal polysilicon 13 a gate 18 is formed. On the p-type silicon substrate 16 is formed an n+ region (region with a high n-type impurity density) 15, on top of which a drain 17 and a source 19 are formed. Note that reference numerals 10, 11, and 12 denote a drain electrode, a gate electrode, and a source electrode, respectively, extending from the drain 17, the gate 18, and the source 19, respectively. In the case of the PMOS transistor, on the other hand, the conduction types of constituent parts of the NMOS transistor shown in FIG. 12 are inverted.
FIG. 13 is a diagram for explaining, using the general sectional structure of the NMOS transistor shown in FIG. 12, a layout and various connections of the switched capacitor circuit unit (NMOS transistors M1 to M4) making up the delay circuit shown in FIG. 10. Note that although a p-type silicon substrate 16a of the switched capacitor unit 703a and a p-type silicon substrate 16c of the switched capacitor unit 703b are shown separately, they are formed on the same silicon wafer. As shown in FIG. 13, with respect to the switched capacitor unit 703a, the NMOS transistors M1 and M2 are disposed adjacent to each other, with their sources 19a and 19b being common. Similarly, with respect to the switched capacitor unit 703b, the NMOS transistors M3 and M4 are disposed adjacent to each other, with their sources 19c and 19d being common. In this manner, generally, the sources 19a and 19b as well as the sources 19c and 19d are respectively disposed in common to achieve integration in terms of layout design (see, e.g., Japanese Patent Laid-Open Publication No. 1997-191472).
Since different p and n conduction types are disposed adjacent to each other between the source and p-type silicon substrate as well as between the drain and the p-type silicon substrate, there potentially exist their respective parasitic capacitances Csb (source-to-substrate) and Cdb (drain-to-substrate). Note that the parasitic capacitances Csb and Cdb are represented as the following equation 1 using the transistor width W and the drain length Ld.Csb=Cdb=(W+α)×(Ld+α)  (1)where α is a coefficient set for each transistor.
In the switched capacitor unit 703a, as shown in FIG. 13, a parasitic capacitance Cdb1 exists between a drain 17a and the p-type silicon substrate 16a, and a parasitic capacitance Cdb2 exists between a drain 17b and the p-type silicon substrate 16a. In the switched capacitor unit 703b, a parasitic capacitance Cdb3 exists between a drain 17c and the p-type silicon substrate 16b, and a parasitic capacitance Cdb4 exists between a drain 17d and the p-type silicon substrate 16b. Note that a parasitic capacitance Csb1 exists between the source 19a, 19b and the p-type silicon substrate 16a, and in the same manner, a parasitic capacitance Csb2 exists between the source 19c, 19d and the p-type silicon substrate 16b, while that a capacitive element C1 is connected to a source electrode 12a, and a capacitive element C2 is connected to a source electrode 12c. That is, it can be said that the parasitic capacitance Csb1 and the capacitive element C1 are connected in parallel and that the parasitic capacitance Csb2 and the capacitive element C2 are connected in parallel. In this case, the capacitive elements C1 and C2 are of the order of picofarad (pF) while the parasitic capacitances Csb1 and Csb2 are of the order of femtofarad (fF) in general, which may be negligible. Therefore, only the drain-to-substrate parasitic capacitances Cdb1 to Cdb4 may be taken into consideration in the delay circuit shown in FIG. 13.
A multiplicity of switched capacitor units 703a and 703b need to be disposed depending on the delay time required as the delay circuit. This results in increased number of drain-to-substrate parasitic capacitances Cdb1 to Cdb4, and combined capacitances in their parallel connections appear on signal paths of the delay circuit. The resultant combined capacitances may then induce problems of dulled final output waveforms of the delay circuit and thus of poor delay characteristics.